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19-4641; Rev 3; 5/09
Two/Four-Channel, I2C Adjustable Current DAC
General Description
The DS4402 and DS4404 contain two and four I 2 C adjustable current DACs, respectively, that are each capable of sinking or sourcing current. Each output has 31 sink and 31 source settings that are programmed by the I2C interface. External resistors set the full-scale range and step size of each output.
Features
Two (DS4402) or Four (DS4404) Current DACs Full-Scale Range for Each DAC Determined by External Resistors 31 Settings Each for Sink and Source Modes I2C-Compatible Serial Interface Two Three-Level Address Pins Allow Nine Devices on Same I2C Bus Small Package (14-Pin TDFN) -40C to +85C Temperature Range 2.7V to 5.5V Operation
DS4402/DS4404
Applications
Power-Supply Adjustment Power-Supply Margining Adjustable Current Sink or Source
Pin Configuration
TOP VIEW
SDA SCL GND FS3 (N.C.) FS2 (N.C.) FS1 FS0 1 2 3 4 5 6 *EP 7 8 OUT0 14 13 12 11 OUT3 (N.C.) VCC OUT2 (N.C.) A1 OUT1 A0
Ordering Information
PART DS4402N+ DS4402N+T&R DS4404N+ DS4404N+T&R TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 14 TDFN-EP* 14 TDFN-EP* 14 TDFN-EP* 14 TDFN-EP*
TDFN (3mm x 3mm x 0.8mm)
*EXPOSED PAD ( ) INDICATES FOR DS4402 ONLY.
+ DS4404/ DS4402
10 9
+Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad.
Typical Operating Circuit
VCC VOUT0 VOUT1 4.7k 4.7k SDA SCL A1 A0 GND VCC DC/DC CONVERTER OUT R0A FB R0B DC/DC CONVERTER FB R1B OUT R1A
DS4402
OUT0 OUT1
FS0 RFS0
FS1 RFS1
______________________________________________ Maxim Integrated Products
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Two/Four-Channel, I2C Adjustable Current DAC DS4402/DS4404
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC, SDA, and SCL Relative to Ground.............................................-0.5V to +6.0V Voltage Range on A0, A1, FS0, FS1, FS2, FS3, OUT0, OUT1, OUT2, and OUT3 Relative to Ground ................-0.5V to (VCC + 0.5V) (Not to exceed 6.0V.) Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature .....................................Refer to IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C.)
PARAMETER Supply Voltage Input Logic 1 (SDA, SCL, A0, A1) Input Logic 0 (SDA, SCL, A0, A1) SYMBOL VCC VIH VIL (Note 1) CONDITIONS MIN 2.7 0.7 x VCC -0.3 TYP MAX 5.5 VCC + 0.3 0.3 x VCC UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER Supply Current Input Leakage (SDA, SCL) Output Leakage (SDA) Output Current Low (SDA) Address Input Resistors Reference Voltage I/O Capacitance SYMBOL ICC I IL IL I OL RIN VREF CI/O VOL = 0.4V VOL = 0.6V 3 6 240 1.23 10 VCC = 5.5V (Note 2) VCC = 5.5V CONDITIONS DS4402 DS4404 MIN TYP MAX 500 500 1 1 UNITS A A A mA k V pF
OUTPUT CURRENT CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER Output Voltage for Sinking Current Output Voltage for Sourcing Current Full-Scale Sink Output Current Full-Scale Source Output Current Output-Current Full-Scale Accuracy Output-Current Temperature Drift SYMBOL VOUT:SINK VOUT:SOURCE IOUT:SINK IOUT:SOURCE I OUT:FS I OUT:TC (Note 3) (Note 3) (Note 3) (Note 3) +25C, VCC = 4.0V; using ideal RFS resistor; VOUT:SINK = 0.5V; VOUT:SOURCE = VCC - 0.8V (Note 4) CONDITIONS MIN 0.5 0 0.5 -2.0 2.5 70 TYP MAX VCC VCC 0.5 2.0 -0.5 5.0 UNITS V V mA mA % ppm/C
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Two/Four-Channel, I2C Adjustable Current DAC
OUTPUT CURRENT CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER Output-Current Power-Supply Rejection Ratio Output Leakage Current at Zero Current Setting Output-Current Differential Linearity Output-Current Integral Linearity I ZERO DNL INL (Note 5) (Note 6) SYMBOL DC -1 CONDITIONS MIN TYP 0.33 +1 0.5 1 MAX UNITS %/V A LSB LSB
DS4402/DS4404
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time START Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tDH:DAT tSU:DAT tSU:STA tR tF tSU:STO CB (Note 8) (Note 8) (Note 8) (Note 7) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF
Note 1: All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative. Note 2: Supply current specified with all outputs set to zero current setting with all inputs (except A1 and A0, which can be open) driven to well-defined logic levels. SDA and SCL are connected to VCC. Excludes current through RFS resistors (IRFS). Total current including IRFS is ICC + (2 x IRFS). Note 3: The output-voltage full-scale current ranges must be satisfied to ensure the device meets its accuracy and linearity specifications. Note 4: Temperature drift excludes drift caused by external resistor. Note 5: Differential linearity is defined as the difference between the expected incremental current increase with respect to position and the actual increase. The expected incremental increase is the full-scale range divided by 31. Note 6: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value. The expected value is a straight line between the zero and the full-scale values proportional to the setting. Note 7: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. Note 8: CB--total capacitance of one bus line in pF.
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Two/Four-Channel, I2C Adjustable Current DAC DS4402/DS4404
Pin Description
PIN DS4404 1 2 3 4 5 6 7 8 10 12 14 9, 11 13 -- -- DS4402 1 2 3 -- -- 6 7 8 10 -- -- 9, 11 13 4, 5, 12, 14 -- NAME SDA SCL GND FS3 FS2 FS1 FS0 OUT0 OUT1 OUT2 OUT3 A0, A1 VCC N.C. EP Address Select Inputs. Tri-level inputs (VCC, GND, N.C.) determine the I2C slave address. See the Detailed Description section for the nine available device addresses. Power Supply No Connection Exposed Pad. Leave unconnected or connect to GND. Current Output. Sinks or sources the current determined by the I2C interface and the resistance connected to FSx. (DS4402 has only two outputs: OUT0 and OUT1.) Full-Scale Calibration Input. A resistor to ground on these pins determines the full-scale current for each output. FS0 controls OUT0, FS1 controls OUT1, etc. (DS4402 has only two inputs: FS0 and FS1.) FUNCTION I2C Serial Data. Input/output for I2C data. I2C Serial Clock. Input for I2C clock. Ground
SDA SCL
A1
A0
VCC
I2C-COMPATIBLE SERIAL INTERFACE
DS4402/DS4404
VCC F8h SOURCE OR SINK MODE GND CURRENT DAC0 F9h 31-POSITIONS EACH FOR SINK AND SOURCE MODE FAh FBh
CURRENT DAC1
CURRENT DAC2
CURRENT DAC3
FS0 RFS0
OUT0
FS1 RFS1
OUT1
FS2 RFS2
OUT2
FS3 RFS3
OUT3
DS4404
Figure 1. Functional Diagram
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Two/Four-Channel, I2C Adjustable Current DAC
Detailed Description
The DS4402/DS4404 contain two/four I2C adjustable current sources (Figure 1) that are each capable of sinking and sourcing current. Each output has 31 sink and 31 source settings that are programmed through the I 2C interface. The full-scale ranges (and corresponding step sizes) of the outputs are determined by external resistors that adjust the output currents over a 4:1 range. The formula to determine the external resistor values (RFS) for each of the outputs is given by: Equation 1: RFS = (VREF / IFS) x (31 / 4) where IFS = desired full-scale current On power-up, the DS4402/DS4404 output zero current. This is done to prevent it from sinking or sourcing an incorrect current before the system host controller has had a chance to modify the device's setting. As a source for biasing instrumentation or other circuits, the DS4402/DS4404 provide a simple and inexpensive current source with an I2C interface for control. The adjustable full-scale range allows the application to get the most out of its 5-bit sink or source resolution. When used in adjustable power-supply applications (see the Typical Operating Circuit), the DS4402/DS4404 do not affect the initial power-up supply voltage because it defaults to providing zero output current on power-up. As it sources or sinks current into the feedback voltage node, it changes the amount of output voltage required by the regulator to reach its steady state operating point. By using the external resistor to set the output current range, the devices provide flexibility for adjusting the impedances of the feedback network or the range over which the power supply can be controlled or margined.
VCC
DS4402/DS4404
RIN A1 A0 RIN
RIN I2C ADDRESS DECODE RIN
Figure 2. I2C Address Inputs
Table 1 lists the slave address determined by the address input combinations.
Table 1. Slave Addresses
A1 GND GND VCC VCC N.C. N.C. GND VCC N.C. A0 GND VCC GND VCC GND VCC N.C. N.C. N.C. SLAVE ADDRESS (HEXADECIMAL) 90h 92h 94h 96h 98h 9Ah 9Ch 9Eh A0h
I2C Slave Address
The DS4402/DS4404 respond to one of nine I2C slave addresses determined by the two tri-level address inputs. The three input states are connected to VCC, connected to ground, or disconnected. To sense the disconnected state (Figure 2), the address inputs have weak internal resistors that pull the pins to mid-supply.
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Two/Four-Channel, I2C Adjustable Current DAC DS4402/DS4404
Memory Organization
To control the DS4402/DS4404's current sources, write to the memory addresses listed in Table 2.
I2C Serial Interface Description
I2C Definitions The following terminology is commonly used to describe I2C data transfers: Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, START and STOP conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 3 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 3 for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See Figure 3 for applicable timing.
Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL, plus the setup and hold time requirements (Figure 3). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 3) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave.
Table 2. Memory Addresses
MEMORY ADDRESS (HEXADECIMAL) F8h F9h FAh* FBh* CURRENT SOURCE OUT0 OUT1 OUT2* OUT3*
*Only for DS4404.
The format of each output control register is given by:
MSB S X X D4 D3 D2 D1 LSB D0
Where:
BIT NAME FUNCTION Determines if DAC sources or sinks current. For sink S = 0, for source S = 1. Reserved. Both bits read zero. 5-Bit Data Word Controlling DAC Output. Setting 00000b outputs zero current regardless of the state of the sign bit. POWER-ON DEFAULT 0b
S
Sign Bit
X
Reserved
00b
DX
Data
00000b
Example: IFS0 = 800A, and register F8h is written to a value of 92h. Calculate the value of external resistance required, and the magnitude of the output current with this register setting. RFS = (VREF / 800A) x (31 / 4) = 11.9k The MSB of the output register is 1, so the output is sourcing the value corresponding to position 12h (18 decimal). The magnitude of the output current is equal to: 800A x (18 / 31) = 465A
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Two/Four-Channel, I2C Adjustable Current DAC
Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the ninth bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the ninth bit. A device performs a NACK by transmitting a one during the ninth bit. Timing for the ACK and NACK is identical to all other bit writes (Figure 4). An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition, and the acknowledgement is read using the bit-read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminated communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS4402/DS4404s' slave address is determined by the state of the A0 and A1 address pins. Table 1 describes the addresses corresponding to the state of A0 and A1. When the R/W bit is 0 (such as in A0h), the master is indicating it will write data to the slave. If R/W = 1 (A1h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS4402/DS4404 assume the master is communicating with another I2C device and ignore the communication until the next START condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.
DS4402/DS4404
I2C Communication Writing to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember that the master must read the slave's acknowledgement during all byte-write operations. Reading from a Slave: To read from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition.
SDA tBUF tF tLOW SCL tHD:STA tSP
tHIGH tHD:STA tR tHD:DAT STOP START tSU:DAT REPEATED START
tSU:STA
tSU:STO
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 3. I2C Timing Diagram
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Two/Four-Channel, I2C Adjustable Current DAC DS4402/DS4404
Applications Information
Example Calculations for an Adjustable Power Supply
Using the typical circuit, assuming a typical output voltage of 2.0V, a feedback voltage of 0.8V, R1 = 500, and R2 = 333, to adjust or margin the supply 20% requires a full-scale current equal to [(0.2 x 2.0V) / 500 = 800A]. Using Equation 1, RFS can be calculated [RFS = (VREF / 800A) x (31 / 4) = 11.9k]. The current DAC in this configuration allows the output voltage to be stepped linearly from 1.6V to 2.4V using 63 settings. This corresponds to a resolution of 12.7mV/step. Changing the address select inputs resets the I2C interface. This function aborts the current transaction and puts the SDA driver into a high-impedance state. This hardware reset function should never be required because it is achievable through software, but it does provide an alternative way of resetting the I2C interface, if needed.
Power-Supply Feedback Voltage
The feedback voltage for adjustable power supplies must be between 0.5V and VCC - 0.5V for the DS4402/ DS4404 to properly sink/source currents for adjusting the voltage.
VCC Decoupling To achieve the best results when using the DS4402/ DS4404, decouple the power supply with a 0.01F or 0.1F capacitor. Use a high-quality ceramic surfacemount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. Layout Considerations
Care should be taken to ensure that traces underneath the DS4402/DS4404 do not short with the exposed pad. The exposed pad should be connected to the signal ground, or can be left unconnected.
I2C Reset on Address Change In addition to defining the I2C slave address, the DS4402/ DS4404 address select inputs have an alternate function.
TYPICAL I2C WRITE TRANSACTION MSB START a7 a6 a5 a4 a3 a2 a1 LSB R/W SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
SLAVE ADDRESS*
READ/ WRITE
REGISTER/MEMORY ADDRESS
DATA
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1 (SEE TABLE 1). EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE N.C.) A0h A) SINGLE BYTE WRITE -WRITE RESISTOR F9h TO 00h B) SINGLE BYTE READ -READ RESISTOR F8h F9h SLAVE 0 0 0 0 0 0 0 0 ACK SLAVE ACK A1h REPEATED START 1 0 1 0 0 0 0 1 SLAVE ACK STOP
START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 1 ACK A0h F8h
DATA MASTER NACK STOP
START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 0 SLAVE ACK ACK
Figure 4. I2C Communication Examples
Chip Information
TRANSISTOR COUNT: 10,992
PACKAGE TYPE 14 TDFN-EP
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE CODE T1433+1 DOCUMENT NO. 21-0137
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Two/Four-Channel, I2C Adjustable Current DAC
Revision History
REVISION NUMBER 0 1 2 3 REVISION DATE 4/06 8/06 10/08 5/09 Initial release. In the Features, corrected the operating range from 1.7V to 5.5V to 2.7V to 5.5V. Added the I/O capacitance (CI/O) parameter to the DC Electrical Characteristics table. In the Output Current Characteristics table, added VOUT:SINK = 0.5V; VOUT:SOURCE = VCC = 0.8V to the IOUT:FS conditions. DESCRIPTION PAGES CHANGED -- 1 2 2
DS4402/DS4404
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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